AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
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SPRS717H –OCTOBER 2011–REVISED MAY 2015
7.7 External Memory Interfaces
The device includes the following external memory interfaces:
• General-purpose memory controller (GPMC)
• mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface (EMIF)
7.7.1 General-Purpose Memory Controller (GPMC)
NOTE
For more information, see the Memory Subsystem and General-Purpose Memory Controller
section of the AM335x Sitara Processors Technical Reference Manual (SPRUH73).
The GPMC is the unified memory controller used to interface external memory devices such as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
7.7.1.1 GPMC and NOR Flash—Synchronous Mode
Table 7-21 and Table 7-22 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-17 through Figure 7-21).
Table 7-20. GPMC and NOR Flash Timing Conditions—Synchronous Mode
PARAMETER MIN TYP MAX UNIT
Input Conditions
t
R
Input signal rise time 1 5 ns
t
F
Input signal fall time 1 5 ns
Output Condition
C
LOAD
Output load capacitance 3 30 pF
Table 7-21. GPMC and NOR Flash Timing Requirements – Synchronous Mode
OPP100 OPP50
NO. UNIT
MIN MAX MIN MAX
F12 t
su(dV-clkH)
Setup time, input data gpmc_ad[15:0] valid before output clock 3.2 13.2 ns
gpmc_clk high
F13 t
h(clkH-dV)
Hold time, input data gpmc_ad[15:0] Industrial extended 4.74 4.74 ns
valid after output clock gpmc_clk temperature
high (-40°C to 125°C)
All other temperature ranges 4.74 2.75
F21 t
su(waitV-clkH)
Setup time, input wait gpmc_wait[x]
(1)
valid before output clock 3.2 13.2 ns
gpmc_clk high
F22 t
h(clkH-waitV)
Hold time, input wait gpmc_wait[x]
(1)
Industrial extended 4.74 4.74 ns
valid after output clock gpmc_clk temperature
high (-40°C to 125°C)
All other temperature ranges 4.74 2.75
(1) In gpmc_wait[x], x is equal to 0 or 1.
Copyright © 2011–2015, Texas Instruments Incorporated Peripheral Information and Timings 127
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