Texas Instruments AM335x Sitara User Manual

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
www.ti.com SPRS717H –OCTOBER 2011–REVISED MAY 2015
7.8 I
2
C
For more information, see the Inter-Integrated Circuit (I
2
C) section of the AM335x Sitara Processors
Technical Reference Manual (SPRUH73).
7.8.1 I
2
C Electrical Data and Timing
Table 7-68. I
2
C Timing Conditions – Slave Mode
STANDARD MODE FAST MODE
PARAMETER UNIT
MIN MAX MIN MAX
Output Condition
C
b
Capacitive load for each bus line 400 400 pF
Table 7-69. Timing Requirements for I
2
C Input Timings
(see Figure 7-68)
STANDARD MODE FAST MODE
NO. UNIT
MIN MAX MIN MAX
1 t
c(SCL)
Cycle time, SCL 10 2.5 µs
Setup time, SCL high before SDA low (for a repeated
2 t
su(SCLH-SDAL)
4.7 0.6 µs
START condition)
Hold time, SCL low after SDA low (for a START and a
3 t
h(SDAL-SCLL)
4 0.6 µs
repeated START condition)
4 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 µs
5 t
w(SCLH)
Pulse duration, SCL high 4 0.6 µs
6 t
su(SDAV-SCLH)
Setup time, SDA valid before SCL high 250 100
(1)
ns
7 t
h(SCLL-SDAV)
Hold time, SDA valid after SCL low 0
(2)
3.45
(3)
0
(2)
0.9
(3)
µs
Pulse duration, SDA high between STOP and START
8 t
w(SDAH)
4.7 1.3 µs
conditions
9 t
r(SDA)
Rise time, SDA 1000 300 ns
10 t
r(SCL)
Rise time, SCL 1000 300 ns
11 t
f(SDA)
Fall time, SDA 300 300 ns
12 t
f(SCL)
Fall time, SCL 300 300 ns
13 t
su(SCLH-SDAH)
Setup time, high before SDA high (for STOP condition) 4 0.6 µs
14 t
w(SP)
Pulse duration, spike (must be suppressed) 0 50 0 50 ns
(1) A fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
su(SDA-SCLH)
≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device stretches the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
r max
+ t
su(SDA-SCLH)
= 1000 + 250 = 1250 ns (according to the
standard-mode I
2
C-Bus Specification) before the SCL line is released.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum t
h(SDA-SCLL)
has only to be met if the device does not stretch the low period [t
w(SCLL)
] of the SCL signal.
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Texas Instruments AM335x Sitara Specifications

General

Brand	Texas Instruments
Model	AM335x Sitara
Category	Processor
Language	English