SPI_CS[x] (In)
SPI_SCLK (In)
SPI_SCLK (In)
SPI_D[x] (SIMO, In)
Bit n-1 Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=0
EPOL=1
POL=0
POL=1
8
3
4
2
1
3
2
5
SPI_CS[x] (In)
SPI_SCLK (In)
SPI_SCLK (In)
SPI_D[x] ( )SIMO, In
Bit n-1 Bit n-2
Bit n-3
Bit 1
Bit 0
PHA=1
EPOL=1
POL=0
POL=1
8
3
2
1
2
3
1
4
5
4
5 5
4
9
1
9
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
www.ti.com
Figure 7-88. SPI Slave Mode Receive Timing
216 Peripheral Information and Timings Copyright © 2011–2015, Texas Instruments Incorporated
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