PHY address LSB for U9 and U15 can be latched incorrectly
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SPRUI97D–May 2017–Revised September 2019
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Known Deficiencies in AM571x IDK EVM
A.14 PHY address LSB for U9 and U15 can be latched incorrectly
The PHY address LSB for U9 and U15 gets determined by the signal level at the PHY's COL pin during
reset release. The PHY has a pull-down resistor connected to this pin to enable latching the value of 0.
Unfortunately, this pin is also connected to one of the RJ-45 connector LEDs that pulls the signal to an
undefined voltage of about 1.4V during the reset time. Therefore, the PHY address can incorrectly latch a
value of 1. The LED circuit should be configured for active-high indication and the connections to the LED
reversed with the cathode connected to ground. This allows the LSB of the address to be properly latched.
Please refer to Section 6 of the TLK1XX Design and Layout Guide Application Report (SLVA531) for more
information. The current software workaround programs the RXLINK pin with a pull-down resistor and then
pulses the PHY reset from a GPIO, to cause it to latch the PHY address correctly.
A.15 3.3-V clamp circuit needs more margin
The 3.3-V clamp circuit is tuned too close such that if the 1.8-V supply is 5% low and the 3.3-V supply is
5% high, the clamp begins conducting. Replacing resistors R897 and R801 with a 24.3-KΩ resistor
provides the proper tolerance, so the circuit will start conducting at a delta voltage of 1.75 V rather than
the current setting of 1.5 V.
A.16 Current PMIC does not provide the mandated power down sequence
The current PMIC does not provide the mandated power down sequence as shown in the AM571x Sitara
Processors Silicon Revision 2.0 Data Manual (SPRS957). Production IDK EVMs contain the TPS6590377
PMIC, which powers off the DDR supply at the wrong time. The default programming has been corrected
in the TPS6590379 PMIC. This part will be used for future builds.
A.17 Power supply droop may cause board reset
The TPS3808G50 voltage supervisor circuit, U105, monitors the main power input and initiates a power-
down sequence, if the main input voltage drops below 4.65V. Since some external power supplies may
droop during rapid changes in load current, this can trigger an unexpected shut-down and restart
sequence that resets the SOC. U105 can be replaced with a TPS3808G33 voltage supervisor device that
triggers at 3.07V. This is still above the minimum input voltage of the PMIC. However, this lower threshold
voltage may require additional capacitance to be added at the input to the PMIC to allow the power-down
sequence to complete before the input voltage collapses.
A.18 AM5718 pin N21 must be connected to 1.8 V, as it is VDDS18V_DDR1 and not N/C
AM5718 pin N21 must be connected to 1.8 V, as it is VDDS18V_DDR1 and is not N/C. The schematic
symbol has this labeled incorrectly.
A.19 VOUT1 is used at 3.3 V, which violates erratum i920
VOUT1 is used at 3.3V, which violates erratum i920. All VOUT ports can only be operated at 1.8 V on
AM571x devices per the device erratum. Operation at 3.3 V may impact long-term reliability. Voltage-level
translators must be used if these signals interface to circuits that require 3.3V signaling levels.
A.20 PMIC OSC16MCAP pin mistakenly grounded
The OSC16MCAP pin on the TPS659037x PMIC should be connected to a 2.2-μF capacitor to ground.
Unfortunately, all versions of this IDK EVM have this pin connected directly to ground. Although there are
many IDK EVMs in use, connecting the OSC16MCAP pin directly to ground may damage the
TPS659037x PMIC. Operation may become erratic or it may fail completely. Designs that copied this
design mistake must be corrected.
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