Overview of Thread Scheduling
Thread Scheduling 4-9
Table 4-2. Thread Preemption
Figure 4-2 shows the execution graph for a scenario in which SWIs and HWIs
are enabled (the default), and a hardware interrupt routine posts a software
interrupt whose priority is higher than that of the software interrupt running
when the interrupt occurs. Also, a second hardware interrupt occurs while the
first ISR is running. The second ISR is held off because the first ISR masks
off (that is, disables) the second interrupt during the first ISR.
Thread Running
Thread Posted HWI SWI TSK IDL
Enabled HWI Preempts Preempts Preempts Preempts
Disabled HWI Waits for
reenable
Waits for
reenable
Waits for
reenable
Waits for
reenable
Enabled, higher-priority SWI —— Preempts Preempts Preempts
Disabled SWI Waits Waits for
reenable
Waits for
reenable
Waits for
reenable
Lower priority SWI Waits Waits —— ——
Enabled, higher-priority TSK —— —— Preempts Preempts
Disabled TSK Waits Waits Waits for
reenable
Waits for
reenable
Lower priority TSK Waits Waits Waits ——
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