DSP/BIOS Startup Sequence
Program Generation 2-27
The C5500 platform also allows for three possible stack modes (see
Table 2-3). To configure the processor in any of the non-default modes, the
user is required to set bits 28 and 29 to the reset vector location appropriately
using the Code Composer Studio debugger tool and then to apply a software
reset. For more information, please see the TMS320C55x DSP CPU
Reference Guide.
Table 2-3. Stack Modes on the C5500 Platform
In addition, the DSP/BIOS configuration should set the Stack Mode property
of the HWI Manager to match the mode used by the application. See the
TMS320C5000 DSP/BIOS API Reference Guide for details.
Stack Mode Description Reset Vector Settings
2x16 Fast Return
SP/SSP independent,
RETA/CFCT used for fast
return functionality
XX00 : XXXX : <24-bit vector address>
2x16 Slow Return
SP/SSP independent,
RETA/CFCT not used
XX01 : XXXX : <24-bit vector address>
1x32 Slow Return
(Reset default)
SP/SSP synchronized,
RETA/CFCT not used
XX02 : XXXX : <24-bit vector address>
To Next Page
Loading...
Need help?
General
