Hardware Interrupts
Thread Scheduling 4-11
4.2 Hardware Interrupts
Hardware interrupts handle critical processing that the application must
perform in response to external asynchronous events. The DSP/BIOS HWI
module is used to manage hardware interrupts.
In a typical DSP system, hardware interrupts are triggered either by on-
device peripherals or by devices external to the DSP. In both cases, the
interrupt causes the processor to vector to the ISR address. The address to
which a DSP/BIOS HWI object causes an interrupt to vector can be a user
routine or the common system HWI dispatcher.
Hardware ISRs can be written using assembly language, C, or a combination
of both. HWI functions are usually written in assembly language for efficiency.
To allow an HWI object’s function to be written completely in C, the system
HWI dispatcher should be used.
All hardware interrupts run to completion. If an HWI is posted multiple times
before its ISR has a chance to run, the ISR runs only one time. For this
reason, you should minimize the amount of code performed by an HWI
function. If the GIE bit is enabled, a hardware interrupt can be preempted by
any interrupt that is enabled by the IEMASK.
If an HWI function calls any of the PIP APIs—PIP_alloc, PIP_free, PIP_get,
PIP_put—the pipe's notifyWriter or notifyReader functions run as part of the
HWI context.
Note:
The interrupt keyword or INTERRUPT pragma must not be used when
HWI objects are used in conjunction with C functions. The
HWI_enter/HWI_exit macros and the HWI dispatcher contain this
functionality, and the use of the C modifier can cause program failure.
4.2.1 Configuring Interrupts
In the base DSP/BIOS configuration, the HWI Manager contains an HWI
object for each hardware interrupt in your DSP.
You can configure the ISR for each hardware interrupt in the DSP. You enter
the name of the ISR that is called in response to a hardware interrupt for the
corresponding HWI object in the .tcf configuration file. DSP/BIOS takes care
of setting up the interrupt table so that each hardware interrupt is handled by
the appropriate ISR. You can also configure the memory segment where the
interrupt table is located.
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