Software Interrupts
Thread Scheduling 4-25
4.3 Software Interrupts
Software interrupts are patterned after hardware ISRs. The SWI module in
DSP/BIOS provides a software interrupt capability. Software interrupts are
triggered programmatically, through a call to a DSP/BIOS API such as
SWI_post. Software interrupts have priorities that are higher than tasks but
lower than hardware interrupts.
The SWI module should not be confused with the SWI instruction that exists
on many processors. The DSP/BIOS SWI module is independent from any
processor-specific software interrupt features.
SWI threads are suitable for handling application tasks that occur at slower
rates or are subject to less severe real-time deadlines than those of hardware
interrupts.
The DSP/BIOS APIs that can trigger or post a software interrupt are:
❏ SWI_andn
❏ SWI_dec
❏ SWI_inc
❏ SWI_or
❏ SWI_post
The SWI Manager controls the execution of all software interrupts. When the
application calls one of the APIs above, the SWI Manager schedules the
function corresponding to the software interrupt for execution. To handle all
software interrupts in an application, the SWI Manager uses SWI objects.
If a software interrupt is posted, it runs only after all pending hardware
interrupts have run. An SWI routine in progress can be preempted at any time
by an HWI; the HWI completes before the SWI handler resumes. On the other
hand, SWI handlers always preempt tasks. All pending software interrupts
run before even the highest priority task is allowed to run. In effect, an SWI
handler is like a task with a priority higher than all ordinary tasks.
Note:
Two things to remember about SWI are:
An SWI handler runs to completion unless it is interrupted by a hardware
interrupt or preempted by a higher priority SWI.
When called within an HWI ISR, the code sequence calling any of the SWI
functions which can trigger or post a software interrupt must be either
wrapped within an HWI_enter/HWI_exit pair or invoked by the HWI
dispatcher.
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