Texas Instruments TMS320

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Hardware Interrupts

Thread Scheduling 4-15

Figure 4-3. The Interrupt Sequence in Debug Halt State

Yes

Interrupt request sent to CPU

Check DBGIER bit

Check IER bit

Clear corresponding IER bit

Empty pipeline

Increment and temporarily store PC

Fetch interrupt vector

Increment SP by 1

Perform automatic context save

Clear corresponding IER bit

Set INTM & DBGM, Clear loop,

EALLOW, IDLESTAT

Load PC with fetch vector

Execute interrupt service routine

Program continues

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