Hardware Interrupts
4-14
Example 4-1. Interrupt Behavior for C28x During Real-Time Mode
MAIN_LOOP:
; Do some stuff
SETC INTM, DBGM
/ Uninterruptible, unhaltable region of code
MOV ACC, @Semaphore
SUB ACC, #1 ;Let’s do "*Semaphore--;" really inefficiently!
MOV @Semaphore, ACC
CLRC INTM, DBGM
; Do some more stuff
B MAIN_LOOP
; By default, INTM and DBGM are set in an ISR so you can’t halt
or interrupt
RT_ISR:
; Do some stuff
MOV ACC, @Semaphore
ADD ACC, #1 ;Let’s do "*Semaphore--;" really inefficiently!
MOV @Semaphore, ACC
; Do some more stuff
IRET
Note:
The code above is safe if the debugger issues a halt; you cannot halt in the
italicized regions above, so the PC will always be at the B MAIN_LOOP
instruction. If the user sets a watchpoint to occur when the address
Semaphore is accessed, the CPU will not be able to halt until after CLRC
INTM, DBGM is executed. The same result will occur if the user sets a
hardware breakpoint on RT_ISR. If the user sets a software breakpoint in
the italicized regions above, the CPU will halt, but the debugger will report
this as an error and indicate that this is an improper operation. In this case,
an atomic C28x instruction, such as DEC or INC, should have been used.
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