Texas Instruments TMS320F28069

113
TMS320F28069 , TMS320F28068 , TMS320F28067 , TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com SPRS698F –NOVEMBER 2010–REVISED MARCH 2016
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TMS320F28064 TMS320F28063 TMS320F28062
Detailed DescriptionCopyright © 2010–2016, Texas Instruments Incorporated
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
Table 6-43. McBSP Switching Characteristics
(1)(2)
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
M1 t
c(CKRX)
Cycle time, CLKR/X CLKR/X int 2P ns
M2 t
w(CKRXH)
Pulse duration, CLKR/X high CLKR/X int D – 5
(3)
D + 5
(3)
ns
M3 t
w(CKRXL)
Pulse duration, CLKR/X low CLKR/X int C – 5
(3)
C + 5
(3)
ns
M4 t
d(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int 0 4
ns
CLKR ext 3 27
M5 t
d(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int 0 4
ns
CLKX ext 3 27
M6 t
dis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
CLKX int 8
ns
CLKX ext 14
M7 t
d(CKXH-DXV)
Delay time, CLKX high to DX valid. CLKX int 9
ns
This applies to all bits except the first bit transmitted. CLKX ext 28
Delay time, CLKX high to DX valid DXENA = 0
CLKX int 8
CLKX ext 14
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
DXENA = 1
CLKX int P + 8
CLKX ext P + 14
M8 t
en(CKXH-DX)
Enable time, CLKX high to DX driven DXENA = 0
CLKX int 0
ns
CLKX ext 6
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
DXENA = 1
CLKX int P
CLKX ext P + 6
M9 t
d(FXH-DXV)
Delay time, FSX high to DX valid DXENA = 0
FSX int 8
ns
FSX ext 14
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode.
DXENA = 1
FSX int P + 8
FSX ext P + 14
M10 t
en(FXH-DX)
Enable time, FSX high to DX driven DXENA = 0
FSX int 0
ns
FSX ext 6
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode
DXENA = 1
FSX int P
FSX ext P + 6