EasyManua.ls Logo

TSN Systems Box 3.0 - Introduction; Hardware; General Description; Technical Description

Default Icon
37 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
TSN Box Development – TSN Box 3.0 Getting Started Guide
Introduction – 4
1 Introduction
This is the manual for the TSN Box Version 3.0, onward referred to as the unit. The document describes the
hardware and software of the TSN Box.
2 Hardware
2.1 General Description
The unitis a high-performance analysis tool for time sensitive networks providing the following features:
Host Intel® Celeron-series System-on-Chip (SoC)
Intel® Celeron
TM
N2930, DC, 1.83/2.16GHz, 2MB L2 Cache
8 GB DDR3 Memory
2x USB2.0 Ports
1x USB3.0 Port
1x 1Gb Ethernet Port
1x USB Serial Terminal Port
2x Isolated Input
2x Isolated Outputs (open-collector)
1x Output Power (non-isolated)
12x Audio Ports (6 x stereo connectors)
8x Outputs channels
4x Input channels
2x High-speed GPI (SMA, 50Ω load impedance)
2x High-speed GPO (SMA, 50Ω source impedance)
Front Panel Reset
Front Panel General Purpose Button
2x Dual 1Gb Modules
Configured as either 2 x 1000BASE-T or 2 x 1000BASE-T1 or none
1x Quad 100Mb Module
Configured as either 4 x 100BASE-T1 or 4 x 100BASE-TX or none
1x SYNC Module
Configured as 2x PPS/SYNC Ports (50Ω) or none
1x CAN Module
Configured as 1x CAN Channel or none
2.2 Technical Description
The unit consists of a base board with multiple module slots that can be configured in different options and
expanded on in future releases. There are 6 module slots in total.
Audio Slot
The Audio Module can be configured with 8 output channels and 4 input channels over 6 stereo 3.5mm connectors.
There are two audio codecs on the Audio Module, one controlled by the FPGA and one controlled by the Host CPU
as an HDA audio device. The input channels share the same connectors and the output channels are multiplexed
and controlled by the FPGA.
Dual 1Gb Slot #1