Xilinx AC701 User Manual

AC701 Evaluation Board www.xilinx.com 85
UG952 (v1.3) April 7, 2015
Appendix C
Master Constraints File Listing
TheAC701 board master Xilinx Design Constraints (XDC) file template provides for
designs targeting the AC701 board. Net names in the constraints listed in the
AC701 Board
XDC File Listing correlate with net names on the AC701 board schematic. You must
identify the appropriate pins and replace the net names in this list with net names in the
user RTL. For more information, see Vivado Design Suite User Guide, Using Constraints
(UG903)
[Ref 12].
Users can refer to the XDC files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface.
The FMC HPC connector J30 is connected to a 2.5V V
CCO
bank. Because each user FMC
card implements customer-specific circuitry, the FMC bank I/O standards must be
uniquely defined by each customer.
Note: The XDC file listed in this appendix might not be the latest version. Always refer to the Artix-7
FPGA AC701 Evaluation Kit website for the latest FPGA pins constraints file.
AC701 Board XDC File Listing
#Clocks
#SYSCLK
set_property PACKAGE_PIN R3 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_P]
set_property PACKAGE_PIN P3 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_N]
#USER CLOCK
set_property PACKAGE_PIN M21 [get_ports USER_CLOCK_P]
set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_P]
set_property PACKAGE_PIN M22 [get_ports USER_CLOCK_N]
set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_N]
#USER SMA CLOCK
set_property PACKAGE_PIN J23 [get_ports USER_SMA_CLOCK_P]
set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_CLOCK_P]
set_property PACKAGE_PIN H23 [get_ports USER_SMA_CLOCK_N]
set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_CLOCK_N]
#SI5324
set_property PACKAGE_PIN M19 [get_ports SI5324_INT_ALM_B]
set_property IOSTANDARD LVCMOS33 [get_ports SI5324_INT_ALM_B]
set_property PACKAGE_PIN B24 [get_ports SI5324_RST_LS_B]
set_property IOSTANDARD LVCMOS25 [get_ports SI5324_RST_LS_B]
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Xilinx AC701 Specifications

General

Brand	Xilinx
Model	AC701
Category	Motherboard
Language	English