Xilinx AC701 - Page 90

Appendix C: Master Constraints File Listing
90 www.xilinx.com AC701 Evaluation Board
UG952 (v1.3) April 7, 2015
set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
set_property PACKAGE_PIN N7 [get_ports DDR3_A10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
set_property PACKAGE_PIN K3 [get_ports DDR3_A9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
set_property PACKAGE_PIN H1 [get_ports DDR3_A8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
set_property PACKAGE_PIN M6 [get_ports DDR3_A7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
set_property PACKAGE_PIN K1 [get_ports DDR3_A6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
set_property PACKAGE_PIN M7 [get_ports DDR3_A5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A5]
set_property PACKAGE_PIN K5 [get_ports DDR3_A4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A4]
set_property PACKAGE_PIN L4 [get_ports DDR3_A3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A3]
set_property PACKAGE_PIN J1 [get_ports DDR3_A2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A2]
set_property PACKAGE_PIN J3 [get_ports DDR3_A1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A1]
set_property PACKAGE_PIN M4 [get_ports DDR3_A0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A0]
#DDR3 BA
set_property PACKAGE_PIN H2 [get_ports DDR3_BA2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
set_property PACKAGE_PIN M1 [get_ports DDR3_BA1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
set_property PACKAGE_PIN N1 [get_ports DDR3_BA0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
#USB UART
set_property PACKAGE_PIN T19 [get_ports USB_UART_TX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_TX]
set_property PACKAGE_PIN U19 [get_ports USB_UART_RX]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RX]
set_property PACKAGE_PIN V19 [get_ports USB_UART_RTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RTS]
set_property PACKAGE_PIN W19 [get_ports USB_UART_CTS]
set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_CTS]
#IIC
set_property PACKAGE_PIN N18 [get_ports IIC_SCL_MAIN]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_SCL_MAIN]
set_property PACKAGE_PIN K25 [get_ports IIC_SDA_MAIN]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_SDA_MAIN]
set_property PACKAGE_PIN R17 [get_ports IIC_MUX_RESET_B]
set_property IOSTANDARD LVCMOS33 [get_ports IIC_MUX_RESET_B]
#PCIE
set_property PACKAGE_PIN K26 [get_ports PCIE_WAKE_B]
set_property IOSTANDARD LVCMOS33 [get_ports PCIE_WAKE_B]
set_property PACKAGE_PIN M20 [get_ports PCIE_PERST]
set_property IOSTANDARD LVCMOS33 [get_ports PCIE_PERST]
set_property PACKAGE_PIN F11 [get_ports PCIE_CLK_QO_P]
set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_P]
set_property PACKAGE_PIN E11 [get_ports PCIE_CLK_QO_N]
set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_N]
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