Xilinx KCU105 User Manual

KCU105 Board User Guide www.xilinx.com 39
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
GTH Bank
225
AH6 MGTHTXP0_225 PCIE_TX3_P A29 PERp3
PCIe Edge
Connector
P1
AH5 MGTHTXN0_225 PCIE_TX3_N A30 PERn3
AH2 MGTHRXP0_225 PCIE_RX3_P B27 PETp3
AH1 MGTHRXN0_225 PCIE_RX3_N B28 PETn3
AG4 MGTHTXP1_225 PCIE_TX2_P A25 PERp2
AG3 MGTHTXN1_225 PCIE_TX2_N A26 PERn2
AF2 MGTHRXP1_225 PCIE_RX2_P B23 PETp2
AF1 MGTHRXN1_225 PCIE_RX2_N B24 PETn2
AE4 MGTHTXP2_225 PCIE_TX1_P A21 PERp1
AE3 MGTHTXN2_225 PCIE_TX1_N A22 PERn1
AD2 MGTHRXP2_225 PCIE_RX1_P B19 PETp1
AD1 MGTHRXN2_225 PCIE_RX1_N B20 PETn1
AC4 MGTHTXP3_225 PCIE_TX0_P A16 PERp0
AC3 MGTHTXN3_225 PCIE_TX0_N A17 PERn0
AB2 MGTHRXP3_225 PCIE_RX0_P B14 PETp0
AB1 MGTHRXN3_225 PCIE_RX0_N B15 PETn0
AB6 MGTREFCLK0P_225 PCIE_CLK_QO_P A13 REFCLK+
AB5 MGTREFCLK0N_225 PCIE_CLK_QO_N A14 REFCLK-
Y6 MGTREFCLK1P_225 NC NA NA
Y5 MGTREFCLK1N_225 NC NA NA
Table 1-9: KCU105 Board FPGA U1 GTH Banks 224 and 225 Connections to PCIe Connector P1 (Cont’d)
Transceiver
Bank
FPGA
(U1) Pin
FPGA (U1) Pin Name
Schematic Net
Name
Connected
Pin
Connected
Pin Name
Connected
Device
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Xilinx KCU105 Specifications

General

Brand	Xilinx
Model	KCU105
Category	Motherboard
Language	English