Xilinx VCU128 - Page 51

• MGTREFCLK1 – SI5328_CLOCK2_C_P/N
• Four GTY transceivers allocated to QSFP3_TX/RX[1:4]_P/N
Quad 131
• MGTREFCLK0 – QSFP4_SI570_CLOCK_P/N
• MGTREFCLK1 – SMA_REFCLK_INPUT_P/N
• Four GTY transceivers allocated to QSFP4_TX/RX[1:4]_P/N
Quad 129
• MGTREFCLK0 - FMCP_HSPC_GBTCLK5_M2C_P/N
• NC
• Four GTY transceivers allocated to FMCP_HSPC_DP[20:23]
Quad 128
• MGTREFCLK0 - FMCP_HSPC_GBTCLK4_M2C_P/N
• NC
• Four GTY transceivers allocated to FMCP_HSPC_DP[16:19]
Quad 127
• MGTREFCLK0 – FMCP_HSPC_GBTCLK3_M2C_P/N
• NC
• Four GTY transceivers allocated to FMCP_HSPC_DP[12:15]
Quad 126
• MGTREFCLK0 – FMCP_HSPC_GBTCLK2_M2C_P/N
• NC
• Four GTY transceivers allocated to FMCP_HSPC_DP[8:11]
Quad 125
• MGTREFCLK0 – FMCP_HSPC_GBTCLK1_M2C_P/N
• NC
• Four GTY transceivers allocated to FMCP_HSPC_DP[4:7]
Quad 124
• MGTREFCLK0 – FMCP_HSPC_GBTCLK0_M2C_P/N
• NC
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 51
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