Xilinx VCU128 - Page 92

Figure 31: SW1 JTAG Settings
X21977-112818
The mode pins sengs on SW1 determine if the Quad SPI ash is used for conguring the
FPGA. DIP switch SW1 also includes a system controller enable switch in posion 1. See the
UltraScale Architecture Conguraon User Guide (UG570) for further details on conguraon
modes.
Chapter 3: Board Component Descriptions
UG1302 (v1.0) December 21, 2018 www.xilinx.com
VCU128 Board User Guide 92
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