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Xilinx Virtex-7 FPGA VC7222 IBERT - Page 17

Xilinx Virtex-7 FPGA VC7222 IBERT
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VC7222 IBERT Getting Started Guide www.xilinx.com 17
UG971 (v5.0) June 12, 2014
Running the GTH IBERT Demonstration
5. In the Select Hardware Target window, the xilinx_tcf cable appears under
Hardware Targets, and the JTAG chain contents of the selected cable appear under
Hardware Devices (Figure 1-12). Select the xilinx_tcf target and keep the JTAG
Clock Frequency at the default value (15 MHz). Click Next.
6. In the Open Hardware Target Summary window, click Finish. The wizard closes and
the Vivado Design Suite opens the hardware target.
X-Ref Target - Figure 1-12
Figure 1-12: Select Hardware Target
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