Xilinx Virtex-7 FPGA VC7222 IBERT - Page 61

VC7222 IBERT Getting Started Guide www.xilinx.com 61
UG971 (v5.0) June 12, 2014
7. In the Sources window, Design Sources should now reflect that the
SuperClock-2 module is part of the example IBERT design (Figure 3-8).
8. Click Run Synthesis in the Flow Navigator, which synthesizes the complete
design (Figure 3-9).
X-Ref Target - Figure 3-8
Figure 3-8: Design Sources File Hierarchy
X-Ref Target - Figure 3-9
Figure 3-9: Run Synthesis
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8*BFBB
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