Xilinx Virtex-7 FPGA VC7222 IBERT - Page 63

VC7222 IBERT Getting Started Guide www.xilinx.com 63
UG971 (v5.0) June 12, 2014
10. When the Synthesized Design opens, select dbg_hub in the Netlist window, then
select the Debug Core Options tab in the Cell Properties window and change the
C_USER_SCAN_CHAIN* option to 2 (Figure 3-11). Click File > Save
Constraints.
X-Ref Target - Figure 3-11
Figure 3-11: Debug Core Options for dbg_hub
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