Xilinx Virtex-7 VC7203 User Manual

70 www.xilinx.com VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
Appendix C: Master Constraints File Listing
set_property PACKAGE_PIN AG2 [get_ports 114_TX3_P]
set_property PACKAGE_PIN AG1 [get_ports 114_TX3_N]
set_property PACKAGE_PIN AD4 [get_ports 114_RX3_P]
set_property PACKAGE_PIN AD3 [get_ports 114_RX3_N]
set_property PACKAGE_PIN AH4 [get_ports 114_TX2_P]
set_property PACKAGE_PIN AH3 [get_ports 114_TX2_N]
set_property PACKAGE_PIN AE6 [get_ports 114_RX2_P]
set_property PACKAGE_PIN AE5 [get_ports 114_RX2_N]
set_property PACKAGE_PIN AJ2 [get_ports 114_TX1_P]
set_property PACKAGE_PIN AJ1 [get_ports 114_TX1_N]
set_property PACKAGE_PIN AF4 [get_ports 114_RX1_P]
set_property PACKAGE_PIN AF3 [get_ports 114_RX1_N]
set_property PACKAGE_PIN AK4 [get_ports 114_TX0_P]
set_property PACKAGE_PIN AK3 [get_ports 114_TX0_N]
set_property PACKAGE_PIN AG6 [get_ports 114_RX0_P]
set_property PACKAGE_PIN AG5 [get_ports 114_RX0_N]
set_property PACKAGE_PIN Y8 [get_ports 115_REFCLK0_P]
set_property PACKAGE_PIN Y7 [get_ports 115_REFCLK0_N]
set_property PACKAGE_PIN AB8 [get_ports 115_REFCLK1_P]
set_property PACKAGE_PIN AB7 [get_ports 115_REFCLK1_N]
set_property PACKAGE_PIN W2 [get_ports 115_TX3_P]
set_property PACKAGE_PIN W1 [get_ports 115_TX3_N]
set_property PACKAGE_PIN Y4 [get_ports 115_RX3_P]
set_property PACKAGE_PIN Y3 [get_ports 115_RX3_N]
set_property PACKAGE_PIN AA2 [get_ports 115_TX2_P]
set_property PACKAGE_PIN AA1 [get_ports 115_TX2_N]
set_property PACKAGE_PIN AA6 [get_ports 115_RX2_P]
set_property PACKAGE_PIN AA5 [get_ports 115_RX2_N]
set_property PACKAGE_PIN AC2 [get_ports 115_TX1_P]
set_property PACKAGE_PIN AC1 [get_ports 115_TX1_N]
set_property PACKAGE_PIN AB4 [get_ports 115_RX1_P]
set_property PACKAGE_PIN AB3 [get_ports 115_RX1_N]
set_property PACKAGE_PIN AE2 [get_ports 115_TX0_P]
set_property PACKAGE_PIN AE1 [get_ports 115_TX0_N]
set_property PACKAGE_PIN AC6 [get_ports 115_RX0_P]
set_property PACKAGE_PIN AC5 [get_ports 115_RX0_N]
set_property PACKAGE_PIN T8 [get_ports 116_REFCLK0_P]
set_property PACKAGE_PIN T7 [get_ports 116_REFCLK0_N]
set_property PACKAGE_PIN V8 [get_ports 116_REFCLK1_P]
set_property PACKAGE_PIN V7 [get_ports 116_REFCLK1_N]
set_property PACKAGE_PIN P4 [get_ports 116_TX3_P]
set_property PACKAGE_PIN P3 [get_ports 116_TX3_N]
set_property PACKAGE_PIN R6 [get_ports 116_RX3_P]
set_property PACKAGE_PIN R5 [get_ports 116_RX3_N]
set_property PACKAGE_PIN R2 [get_ports 116_TX2_P]
set_property PACKAGE_PIN R1 [get_ports 116_TX2_N]
set_property PACKAGE_PIN U6 [get_ports 116_RX2_P]
set_property PACKAGE_PIN U5 [get_ports 116_RX2_N]
set_property PACKAGE_PIN V4 [get_ports 116_RX1_P]
set_property PACKAGE_PIN T4 [get_ports 116_TX1_P]
set_property PACKAGE_PIN T3 [get_ports 116_TX1_N]
set_property PACKAGE_PIN V3 [get_ports 116_RX1_N]
set_property PACKAGE_PIN U2 [get_ports 116_TX0_P]
set_property PACKAGE_PIN U1 [get_ports 116_TX0_N]
set_property PACKAGE_PIN W6 [get_ports 116_RX0_P]
set_property PACKAGE_PIN W5 [get_ports 116_RX0_N]
set_property PACKAGE_PIN K8 [get_ports 117_REFCLK0_P]
set_property PACKAGE_PIN K7 [get_ports 117_REFCLK0_N]
set_property PACKAGE_PIN M8 [get_ports 117_REFCLK1_P]
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Xilinx Virtex-7 VC7203 Specifications

General

FPGA Family	Virtex-7
Transceiver	GTH
GTH Transceivers	16
Maximum Data Rate	13.1 Gbps
Transceivers	16
Maximum Transceiver Speed	13.1 Gbps
Maximum User I/O	600
Process Technology	28nm
Block RAM	38 Mb
Power Supply Voltage	0.9V
Operating Temperature Range	Industrial