Xilinx Virtex-7 VC7203 User Manual

VC7203 GTX Transceiver Characterization Board www.xilinx.com 71
UG957 (v1.3) October 17, 2014
VC7203 Board XDC Listing
set_property PACKAGE_PIN M7 [get_ports 117_REFCLK1_N]
set_property PACKAGE_PIN K4 [get_ports 117_TX3_P]
set_property PACKAGE_PIN K3 [get_ports 117_TX3_N]
set_property PACKAGE_PIN J6 [get_ports 117_RX3_P]
set_property PACKAGE_PIN J5 [get_ports 117_RX3_N]
set_property PACKAGE_PIN L2 [get_ports 117_TX2_P]
set_property PACKAGE_PIN L1 [get_ports 117_TX2_N]
set_property PACKAGE_PIN L6 [get_ports 117_RX2_P]
set_property PACKAGE_PIN L5 [get_ports 117_RX2_N]
set_property PACKAGE_PIN M4 [get_ports 117_TX1_P]
set_property PACKAGE_PIN M3 [get_ports 117_TX1_N]
set_property PACKAGE_PIN N6 [get_ports 117_RX1_P]
set_property PACKAGE_PIN N5 [get_ports 117_RX1_N]
set_property PACKAGE_PIN N2 [get_ports 117_TX0_P]
set_property PACKAGE_PIN N1 [get_ports 117_TX0_N]
set_property PACKAGE_PIN P8 [get_ports 117_RX0_P]
set_property PACKAGE_PIN P7 [get_ports 117_RX0_N]
set_property PACKAGE_PIN E10 [get_ports 118_REFCLK0_P]
set_property PACKAGE_PIN E9 [get_ports 118_REFCLK0_N]
set_property PACKAGE_PIN G10 [get_ports 118_REFCLK1_P]
set_property PACKAGE_PIN G9 [get_ports 118_REFCLK1_N]
set_property PACKAGE_PIN F4 [get_ports 118_TX3_P]
set_property PACKAGE_PIN F3 [get_ports 118_TX3_N]
set_property PACKAGE_PIN E6 [get_ports 118_RX3_P]
set_property PACKAGE_PIN E5 [get_ports 118_RX3_N]
set_property PACKAGE_PIN G2 [get_ports 118_TX2_P]
set_property PACKAGE_PIN G1 [get_ports 118_TX2_N]
set_property PACKAGE_PIN F8 [get_ports 118_RX2_P]
set_property PACKAGE_PIN F7 [get_ports 118_RX2_N]
set_property PACKAGE_PIN H4 [get_ports 118_TX1_P]
set_property PACKAGE_PIN H3 [get_ports 118_TX1_N]
set_property PACKAGE_PIN G6 [get_ports 118_RX1_P]
set_property PACKAGE_PIN G5 [get_ports 118_RX1_N]
set_property PACKAGE_PIN J2 [get_ports 118_TX0_P]
set_property PACKAGE_PIN H8 [get_ports 118_RX0_P]
set_property PACKAGE_PIN J1 [get_ports 118_TX0_N]
set_property PACKAGE_PIN H7 [get_ports 118_RX0_N]
set_property PACKAGE_PIN A10 [get_ports 119_REFCLK0_P]
set_property PACKAGE_PIN A9 [get_ports 119_REFCLK0_N]
set_property PACKAGE_PIN C10 [get_ports 119_REFCLK1_P]
set_property PACKAGE_PIN C9 [get_ports 119_REFCLK1_N]
set_property PACKAGE_PIN B4 [get_ports 119_TX3_P]
set_property PACKAGE_PIN B3 [get_ports 119_TX3_N]
set_property PACKAGE_PIN A6 [get_ports 119_RX3_P]
set_property PACKAGE_PIN A5 [get_ports 119_RX3_N]
set_property PACKAGE_PIN C2 [get_ports 119_TX2_P]
set_property PACKAGE_PIN C1 [get_ports 119_TX2_N]
set_property PACKAGE_PIN B8 [get_ports 119_RX2_P]
set_property PACKAGE_PIN B7 [get_ports 119_RX2_N]
set_property PACKAGE_PIN D4 [get_ports 119_TX1_P]
set_property PACKAGE_PIN D3 [get_ports 119_TX1_N]
set_property PACKAGE_PIN C6 [get_ports 119_RX1_P]
set_property PACKAGE_PIN C5 [get_ports 119_RX1_N]
set_property PACKAGE_PIN E2 [get_ports 119_TX0_P]
set_property PACKAGE_PIN E1 [get_ports 119_TX0_N]
set_property PACKAGE_PIN D8 [get_ports 119_RX0_P]
set_property PACKAGE_PIN D7 [get_ports 119_RX0_N]
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Xilinx Virtex-7 VC7203 Specifications

General

FPGA Family	Virtex-7
Transceiver	GTH
GTH Transceivers	16
Maximum Data Rate	13.1 Gbps
Transceivers	16
Maximum Transceiver Speed	13.1 Gbps
Maximum User I/O	600
Process Technology	28nm
Block RAM	38 Mb
Power Supply Voltage	0.9V
Operating Temperature Range	Industrial