Xilinx ZC706

ZC706 Evaluation Board User Guide www.xilinx.com 102
UG954 (v1.5) September 10, 2015
ZC706 Evaluation Board XDC Listing
set_property PACKAGE_PIN T5 [get_ports PCIE_RX1_N]
set_property PACKAGE_PIN T6 [get_ports PCIE_RX1_P]
set_property PACKAGE_PIN U3 [get_ports PCIE_RX2_N]
set_property PACKAGE_PIN U4 [get_ports PCIE_RX2_P]
set_property PACKAGE_PIN V5 [get_ports PCIE_RX3_N]
set_property PACKAGE_PIN V6 [get_ports PCIE_RX3_P]
set_property PACKAGE_PIN N3 [get_ports PCIE_TX0_N]
set_property PACKAGE_PIN N4 [get_ports PCIE_TX0_P]
set_property PACKAGE_PIN P1 [get_ports PCIE_TX1_N]
set_property PACKAGE_PIN P2 [get_ports PCIE_TX1_P]
set_property PACKAGE_PIN R3 [get_ports PCIE_TX2_N]
set_property PACKAGE_PIN R4 [get_ports PCIE_TX2_P]
set_property PACKAGE_PIN T1 [get_ports PCIE_TX3_N]
set_property PACKAGE_PIN T2 [get_ports PCIE_TX3_P]
#DDR3
set_property PACKAGE_PIN E10 [get_ports PL_DDR3_A0]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A0]
set_property PACKAGE_PIN B9 [get_ports PL_DDR3_A1]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A1]
set_property PACKAGE_PIN E11 [get_ports PL_DDR3_A2]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A2]
set_property PACKAGE_PIN A9 [get_ports PL_DDR3_A3]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A3]
set_property PACKAGE_PIN D11 [get_ports PL_DDR3_A4]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A4]
set_property PACKAGE_PIN B6 [get_ports PL_DDR3_A5]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A5]
set_property PACKAGE_PIN F9 [get_ports PL_DDR3_A6]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A6]
set_property PACKAGE_PIN E8 [get_ports PL_DDR3_A7]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A7]
set_property PACKAGE_PIN B10 [get_ports PL_DDR3_A8]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A8]
set_property PACKAGE_PIN J8 [get_ports PL_DDR3_A9]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A9]
set_property PACKAGE_PIN D6 [get_ports PL_DDR3_A10]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A10]
set_property PACKAGE_PIN B7 [get_ports PL_DDR3_A11]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A11]
set_property PACKAGE_PIN H12 [get_ports PL_DDR3_A12]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A12]
set_property PACKAGE_PIN A10 [get_ports PL_DDR3_A13]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A13]
set_property PACKAGE_PIN G11 [get_ports PL_DDR3_A14]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A14]
set_property PACKAGE_PIN C6 [get_ports PL_DDR3_A15]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_A15]
set_property PACKAGE_PIN F8 [get_ports PL_DDR3_BA0]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_BA0]
set_property PACKAGE_PIN H7 [get_ports PL_DDR3_BA1]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_BA1]
set_property PACKAGE_PIN A7 [get_ports PL_DDR3_BA2]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_BA2]
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