Xilinx ZC706 User Manual

ZC706 Evaluation Board User Guide www.xilinx.com 22
UG954 (v1.5) September 10, 2015
Feature Descriptions
The ZC706 DDR3 SODIMM interface adheres to the constraints guidelines documented in
the “Dynamic Memory” section of the Zynq-7000 All Programmable SoC PCB Design and Pin
Planning Guide (UG933
). The ZC706 DDR3 SODIMM interface is a 40Ω impedance
implementation. For more details, see the MT8JTF12864HZ-1G6G1 data sheet [Ref 34].
DDR3 Component Memory (PS)
[Figure 1-2, callout 3]
The 1 GB, 32-bit wide DDR3 component memory system is comprised of four 256 Mb x 8
SDRAMs (Micron MT41J256M8HX-15E) at U2-U5. This memory system is connected to the
XC7Z045 AP SoC Processing System (PS) memory interface bank 502. The DDR3 0.75V VTT
termination voltage is sourced from linear regulator U27. The connections between the
DDR3 component memory and XC7Z045 AP SoC bank 502 are listed in Table 1-5.
E7 PL_DDR3_CAS_B SSTL15 115 CAS_B
H11 PL_DDR3_RAS_B SSTL15 110 RAS_B
D10 PL_DDR3_CKE0 SSTL15 73 CKE0
C7 PL_DDR3_CKE1 SSTL15 74 CKE1
F10 PL_DDR3_CLK0_N DIFF_SSTL15 103 CK0_N
G10 PL_DDR3_CLK0_P DIFF_SSTL15 101 CK0_P
D8 PL_DDR3_CLK1_N DIFF_SSTL15 104 CK1_N
D9 PL_DDR3_CLK1_P DIFF_SSTL15 102 CK1_P
Table 1-5: DDR3 Component Memory Connections to the XC7Z045 AP SoC
XC7Z045 (U1) Pin Net Name
Component Memory
Pin Number Pin Name Ref. Des.
E26 PS_DDR3_DQ0 B3 DQ0 U2
A25 PS_DDR3_DQ1 C7 DQ1 U2
E27 PS_DDR3_DQ2 C2 DQ2 U2
E25 PS_DDR3_DQ3 C8 DQ3 U2
D26 PS_DDR3_DQ4 E3 DQ4 U2
B25 PS_DDR3_DQ5 E8 DQ5 U2
D25 PS_DDR3_DQ6 D2 DQ6 U2
B27 PS_DDR3_DQ7 E7 DQ7 U2
A27 PS_DDR3_DQ8 B3 DQ8 U3
A28 PS_DDR3_DQ9 C7 DQ9 U3
A29 PS_DDR3_DQ10 C2 DQ10 U3
Table 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont ’d)
XC7Z045 (U1)
Pin
Net Name I/O Standard
DDR3 SODIMM Memory J1
Pin Number Pin Name
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Xilinx ZC706 Specifications

General

Brand	Xilinx
Model	ZC706
Category	Motherboard
Language	English