ZC706 Evaluation Board User Guide www.xilinx.com 87
UG954 (v1.5) September 10, 2015
Jumpers
Jumpers
[Figure 1-2, callout 24]
Default jumper positions are listed in Table A-2.
Table A-2: Default Jumper Settings
Jumper
Callout
Jumper Function
Default Jumper
Position
Option Selected
Schematic
0381513
Page
HDR_1 X 2
1J6
J65
AP SoC U1 Bank 0 CFGBVS pin V9 logic 0/1 Select
(call out #1 applies to this, too):
J65 is an INIT_B (pin 1) and DONE (pin 2) test
header
OPEN
OPEN
CFGBVS pin V9 = 1
N/A
3
3
2 J7 U8 MAX16025 POR Device Reset MR_B pin 13 logic
0/1 Select
OPEN U8 MR_B pin 13 = 1 15
3 J8 JTAG Header J62 pin 2 can be connected to 3.3V OPEN J62 pin 2 is NC 16
4 J9 U51 Ethernet PHY CONFIG2 pin 2 1K pull-down to
logic 0 (GND)
1-2 U51 pin 2 CONFIG2 = 0
5 J10 U12 USB3320 2.0 Host/OTG or Device Select
Header
1-2 HOST source VBUS power
(from U22)
31
6 J11 U12 USB3320 2.0 RESET Header OPEN U12 not held in RESET 31
7 J12 U38 REF3012 VREF XADC_AGND-to-GND L3
inductor bypass
OPEN L3 not bypassed 35
8 J13 U38 REF3012 VREF XADC_AGND-to-GND Select
Header
1-2 XADC_AGND connected to
GND
35
9 J14 XADC circuit VCC5V0 sources XADC_VCC5V0 Select
Header
1-2 XADC_VCC5V0 = filtered
(L1) VCC5V0
35
10 J15 ARM PJTAG Header J64 pin 2 can be connected to
VADJ
OPEN J64 pin 2 is NC 39
11 J17 SPF+ P2 pin 3 SFP_TX_DISABLE_TRANS logic 0/1
Select Header
OPEN SPF+ P2 SFP TX is enabled
(P2 pin 3 = 1)
41
12 J18 FMC_VADJ_ON_B Select Header 1-2 FMC VADJ enabled (U48
UCD90120A pin 37 = logic
0)
49
13 J19 PCIe® Lane Width Select Header 3-4 4-Lane PCIe selected 42
14 J66 PL_PWR_ON Header OPEN PL Power enabled
(U48 UCD90120A pin 24 =
logic 1)
49
15 J69 XADC Power System Vccint CS OpAmp U69 Gain
Select Header
OPEN U69 Current Sense OpAmp
Gain = 10
45
16 J70 MIO Select Header MIO2 (Note: DIP SW11 pole 1
affects this signal)
1-2 QSPI0_IO0 = MIO2_SELECT 15
17 J71 MIO Select Header MIO3 (Note: DIP SW11 pole 2
affects this signal)
1-2 QSPI0_IO1 = MIO3_SELECT 15
To Next Page
Loading...
Need help?
General
