Xilinx ZC706 User Manual

ZC706 Evaluation Board User Guide www.xilinx.com 106
UG954 (v1.5) September 10, 2015
ZC706 Evaluation Board XDC Listing
set_property PACKAGE_PIN L8 [get_ports PL_DDR3_DQS4_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS4_P]
set_property PACKAGE_PIN F12 [get_ports PL_DDR3_DQS5_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS5_N]
set_property PACKAGE_PIN G12 [get_ports PL_DDR3_DQS5_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS5_P]
set_property PACKAGE_PIN E17 [get_ports PL_DDR3_DQS6_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS6_N]
set_property PACKAGE_PIN F17 [get_ports PL_DDR3_DQS6_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS6_P]
set_property PACKAGE_PIN A15 [get_ports PL_DDR3_DQS7_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS7_N]
set_property PACKAGE_PIN B15 [get_ports PL_DDR3_DQS7_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_DQS7_P]
set_property PACKAGE_PIN E7 [get_ports PL_DDR3_CAS_B]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_CAS_B]
set_property PACKAGE_PIN D10 [get_ports PL_DDR3_CKE0]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_CKE0]
set_property PACKAGE_PIN C7 [get_ports PL_DDR3_CKE1]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_CKE1]
set_property PACKAGE_PIN F10 [get_ports PL_DDR3_CLK0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_CLK0_N]
set_property PACKAGE_PIN G10 [get_ports PL_DDR3_CLK0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_CLK0_P]
set_property PACKAGE_PIN D8 [get_ports PL_DDR3_CLK1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_CLK1_N]
set_property PACKAGE_PIN D9 [get_ports PL_DDR3_CLK1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports PL_DDR3_CLK1_P]
set_property PACKAGE_PIN G7 [get_ports PL_DDR3_ODT0]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_ODT0]
set_property PACKAGE_PIN C9 [get_ports PL_DDR3_ODT1]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_ODT1]
set_property PACKAGE_PIN H11 [get_ports PL_DDR3_RAS_B]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_RAS_B]
set_property PACKAGE_PIN G17 [get_ports PL_DDR3_RESET_B]
set_property IOSTANDARD LVCMOS15 [get_ports PL_DDR3_RESET_B]
set_property PACKAGE_PIN J11 [get_ports PL_DDR3_S0_B]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_S0_B]
set_property PACKAGE_PIN H8 [get_ports PL_DDR3_S1_B]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_S1_B]
set_property PACKAGE_PIN M10 [get_ports PL_DDR3_TEMP_EVENT]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_TEMP_EVENT]
set_property PACKAGE_PIN F7 [get_ports PL_DDR3_WE_B]
set_property IOSTANDARD SSTL15 [get_ports PL_DDR3_WE_B]
#PLJTAG
set_property PACKAGE_PIN AK13 [get_ports PL_PJTAG_TCK]
set_property IOSTANDARD LVCMOS25 [get_ports PL_PJTAG_TCK]
set_property PACKAGE_PIN AH18 [get_ports PL_PJTAG_TDI]
set_property IOSTANDARD LVCMOS25 [get_ports PL_PJTAG_TDI]
set_property PACKAGE_PIN AA13 [get_ports PL_PJTAG_TDO_R]
set_property IOSTANDARD LVCMOS25 [get_ports PL_PJTAG_TDO_R]
set_property PACKAGE_PIN AK12 [get_ports PL_PJTAG_TMS]
set_property IOSTANDARD LVCMOS25 [get_ports PL_PJTAG_TMS]
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Xilinx ZC706 Specifications

General

Brand	Xilinx
Model	ZC706
Category	Motherboard
Language	English