Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 116
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN AL7 [get_ports "USER_SI570_N"]
set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_N"]
set_property PACKAGE_PIN AL8 [get_ports "USER_SI570_P"]
set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_P"]
set_property PACKAGE_PIN R9 [get_ports "SFP_REC_CLOCK_C_N"]
set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_N"]
set_property PACKAGE_PIN R10 [get_ports "SFP_REC_CLOCK_C_P"]
set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_P"]
set_property PACKAGE_PIN AG4 [get_ports "HDMI_REC_CLOCK_C_N"]
set_property IOSTANDARD LVDS [get_ports "HDMI_REC_CLOCK_C_N"]
set_property PACKAGE_PIN AG5 [get_ports "HDMI_REC_CLOCK_C_P"]
set_property IOSTANDARD LVDS [get_ports "HDMI_REC_CLOCK_C_P"]
set_property PACKAGE_PIN AG6 [get_ports "HDMI_TX_LVDS_OUT_N"]
set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_N"]
set_property PACKAGE_PIN AF6 [get_ports "HDMI_TX_LVDS_OUT_P"]
set_property IOSTANDARD LVDS [get_ports "HDMI_TX_LVDS_OUT_P"]
#For completeness, the MGT clocks are documented here:
#MGTH 128 HDMI I/F
set_property PACKAGE_PIN R27 [get_ports "HDMI_SI5324_OUT_C_P"]
set_property PACKAGE_PIN R28 [get_ports "HDMI_SI5324_OUT_C_N"]
set_property PACKAGE_PIN N27 [get_ports "HDMI_RX_CLK_C_P"]
set_property PACKAGE_PIN N28 [get_ports "HDMI_RX_CLK_C_N"]
#MGTH 129 HPC1_DP[4:7]
set_property PACKAGE_PIN L27 [get_ports "USER_MGT_SI570_CLOCK1_C_P"]
set_property PACKAGE_PIN L28 [get_ports "USER_MGT_SI570_CLOCK1_C_N"]
set_property PACKAGE_PIN J27 [get_ports "USER_SMA_MGT_CLOCK_C_P"]
set_property PACKAGE_PIN J28 [get_ports "USER_SMA_MGT_CLOCK_C_N"]
#MGTH 130 HPC1_DP[0:3]
set_property PACKAGE_PIN G27 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_P"]
set_property PACKAGE_PIN G28 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_N"]
set_property PACKAGE_PIN E27 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_P"]
set_property PACKAGE_PIN E28 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_N"]
# MGTH 228 HPC0_DP[4:6]
set_property PACKAGE_PIN L8 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_P"]
set_property PACKAGE_PIN L7 [get_ports "FMC_HPC0_GBTCLK1_M2C_C_N"]
#MGTH 229 HPC0_DP[0:3]
set_property PACKAGE_PIN G8 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_P"]
set_property PACKAGE_PIN G7 [get_ports "FMC_HPC0_GBTCLK0_M2C_C_N"]
#MGTH 230 SFP0 I/F
set_property PACKAGE_PIN C8 [get_ports "USER_MGT_SI570_CLOCK2_C_P"]
set_property PACKAGE_PIN C7 [get_ports "USER_MGT_SI570_CLOCK2_C_N"]
set_property PACKAGE_PIN B10 [get_ports "SFP_SI5328_OUT_C_P"]
set_property PACKAGE_PIN B9 [get_ports "SFP_SI5328_OUT_C_N"]
#GTR 505 FIXED CLOCKS SOURCED FROM U69 SI5341B
#Other net PACKAGE_PIN AA27 - GTR_REF_CLK_PCIE_C_P
#Other net PACKAGE_PIN AA28 - GTR_REF_CLK_PCIE_C_N
#Other net PACKAGE_PIN W27 - GTR_REF_CLK_SATA_C_P
#Other net PACKAGE_PIN W28 - GTR_REF_CLK_SATA_C_N
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux