ZCU102 Evaluation Board User Guide www.xilinx.com 7
UG1182 (v1.2) March 20, 2017
Chapter 1: Introduction
Block Diagram
The ZCU102 board block diagram is shown in Figure 1-1. Page numbers in the block
diagram reference the corresponding page number(s) of schematic 0381701.
X-Ref Target - Figure 1-1
Figure 1-1: ZCU102 Evaluation Board Block Diagram
Prototype Header
Display Port Aux
MSP430 GPIO IIC0
Connection
Pages 44, 56, 38
SYSMON IIC
SFP Disables
MSP430/CP2108 UART
HDMI control
Pages 6, 34
PMOD
125MHz CLK
Trace
IIC1 Connection
Pages 54-55, 58
Ethernet
USB
Pages 51-52
SDIO
PMU, GPIO
PS Display Port Aux
Pages 47, 44-45
FMC HPC1
GT Interface
Pages 30-33
HDMI
SMA
Pages 35-37, 40
SFP 2x2 Cage
Page 34
FMC HPC0
GT Interface
Pages 26-29
FMC HPC0
LA Bus
Pages 26-29
FMC HPC0
LA Bus
Pages 41-43
FMC HPC1
LA Bus
Pages 30-33
HDMI TX Clock
Pages 35-37
DDR4 Comp.
Memory
16-bit: 1 x 16-bit
MT40A256M16GE-075E
Pages 26-29
SFP Recovered
Clock
Page 34
HDMI Recovered
Clock
Pages 35-37
MUX connections:
PCIe / DisplayPort
USB3.0 / SATA
Pages 43-45, 48, 51
INIT, DONE LEDs
PROG. PB
PS POR, SRST PBs
Page 12
SI570
Programmable
Oscillator
Page 40
BPIO
74.25MHz clk
Page 39
PS UART
PS I2C
PS QSPI
Pages 42, 46, 57-58
DDR4 72-bit
S0DIMM
Page 23
DDR4 DIMM
DECOUPLING
Page 24
JTAG CONN.
Page 22
GTR Muxes
Page 45
PS/PL/System
Clock devices
Pages 39-41
MECHANICALS
Page 87
GTH230
GTH229
GTH228
66
HP
65
HP
64
HP
49
50
48 47
PS
502
PS
501
PS
503
(PS-Side
CONFIG)
GTH130
GTH129
GTH128
PS
GTR505
67
HP
U1
0
44
PS
500
PS
504
PS DDR
PS PWR
XCZU9EGFFVB1156
;
To Next Page
Loading...
Need help?
General
