Yamaha QL5 - Page 303

HG F E D C B A
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5
QL5/QL1
BLOCK DIAGRAM 003 (QL5/QL1)
BLOCK DIAGRAM 003 (QL5/QL1)
28CA1-2001135745-3
CPU, LCDC, USB, 10.4" LCD
OSC
27.2MHz
+1.8D
+3.3D
DC-DC
+1.2D
+1.8D
RESET
(3.0V)
RESET
(2.9V)
CPLD
Address Decode
Wait Control
E-Bus BUSY
IRQ OR
DDR2-SDRAM
1Gbit x2
+3.3D
+3.3D
+3.3D
MRAM
1Mbit
FlashROM
512Mbit
(MAC Address Inside)
E-Bus
Controller
+3.3D
+3.3D
+3.3D
BUFFER
+3.3D
LVDS Tx
+3.3D
10/100Base
PHY
+3.3D
OSC
50MHz
+3.3D
OSC
48MHz
+3.3D
RTC
+3.3B
+3.3B
+3.3D
CPU
SH7724
+3.3D
+1.2D
Xtal
32.768KHz
32bit
+1.8D
tib61tib61 8bit
CKO
/WAIT
IRQ
CPU Bus
LCDC
LCD module
with
Touch Panel
16bit
PORT
I2C
RMII
/IRQ_MY x3
/WAIT
CKO LCDDON
Ethernet
(Editor)
A[1:24]
D[0:15]
E-Bus
Wired OR
/SYSRES
SCI x3
I2C
USB
Hub
+3.3D
Xtal
12MHz
USB
USB
Power
Switch
+5D
CPU
M38039
CERALOCK
16MHz
Touch Panel
Position Detect
(Tr. x5, AND x2)
AD
PORT
+5D
SCI
DS US
/SYSRES
See page 4
PORT
SCISPI I2C
Battery Backup
& Check
(Comparator, Diode, FET)
SPI
LED(BL)
Driver
+5D
+12D
PORT
USB
USB
PORT
PORT
PORT
FSI
Fs, 64Fs
(Master Clock)
TDM
(2ch/line)
/RES_IN
+5D
+12D
+24D
DC-DC
+24D
+3.3L
See page 9
8bit
IRQ x5
IRQ
CPU Bus
CAUTIONS(DCMS), ...
PORT RESETS, ...
IN :
OUT :
CPU Core :
DDR2-SDRAM :
BUS :
489.6MHz
163.2MHz
81.6MHz
2 MAC Addresses inside
LCDC
DCM
CPUQL
QL5
DSP32
QL1
DSP16
USB
CN202
(4P)
CN201
(5P)
IC201
(48P)
IC203(5P)
IC103(5P)
IC202(100P)
IC203(20P)IC204(44P)
IC401(48P)
IC602-607
(20P)
IC402
(33P)
IC205(56P)
IC301, 302
IC104(8P)
BT501
D501, D502, FT501, FT510
IC503(5P)
IC502
(10P)
IC201(8P)
IC106(5P)
IC105(25P)
X101
X501
X404
X401
IC101
CN103
(5P)
CN101(180P)
CN301(180P)
CN102
(6P)
CN101
(9P)
CN281(4P)
CN1(20P)
CN151(6P)
CN102(5P),
CN150(4P)
CN101
(6P)
CN402
(20P)
CN203
X201