Alinx AXKU15 - Part 3.8: SATA Interface

AXKU15 User Manual
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SD_CLK
B91_L8_P
C10
SD clock signal
SD_CMD
B91_L8_N
C9
SD command signal
SD_D0
B90_L12_N
A6
SD Data 0
SD_D1
B90_L12_P
B6
SD Data 1
SD_D2
B91_L7_N
C7
SD Data 2
SD_D3
B91_L7_P
C8
SD Data 3
Table 23: SD card slot pin assignment
Part 3.8: SATA Interface
The board is equipped with two SATA interfaces, and the differential signal of SATA is connected to GTY BANK131.
The SATA reference clock of 150Mhz is provided by the programmable clock chip Si5332BD11025-4. The schematic
diagram of SATA interface design is shown in Figure 25 below:
Figure 25: SATA Interface Design Diagram
The SATA interface FPGA pin assignments are as follows:
Signal name
Pin name
Pin number
Remark
SATA1_RX_N
MGT131_RX0_N
M37
SATA1 data receive negative
SATA1_RX_P
MGT131_RX0_P
M36
SATA 1 data receiving positive
SATA2_RX_N
MGT131_RX1_N
L39
SATA2 data reception is negative
SATA2_RX_P
MGT131_RX1_P
L38
SATA2 data receiving positive
SATA1_TX_N
MGT131_TX0_N
J34
SATA 1 Data Transmit Negative
SATA1_TX_P
MGT131_TX0_P
J33
SATA 1 Data Sending Positive
SATA2_TX_N
MGT131_TX1_N
G34
SATA2 data transmission is negative
SATA2_TX_P
MGT131_TX1_P
G33
SATA2 Data Sending Positive
SATACLK_N
MGT131_CLK0_N
T28
SATA Reference Clock Negative
SATACLK_P
MGT131_CLK0_P
T27
SATA reference clock positive
Table 24: SATA interface pin assignment