Alinx AXU4EV-E - Part 2.4: QSPI Flash

ZYNQ Ultrascale + FPGA Board AXU4EV-E User Manual
20 / 58
Amazon Store: https://www.amazon.com/alinx
PL_DDR4_A7
IO_L2P_T0L_N2_64
AE9
PL_DDR4_A8
IO_L9P_T1L_N4_AD12P_64
AH8
PL_DDR4_A9
IO_L1P_T0L_N0_DBC_64
AC9
PL_DDR4_A10
IO_L4N_T0U_N7_DBC_AD7N_64
AE7
PL_DDR4_A11
IO_L7N_T1L_N1_QBC_AD13N_64
AH9
PL_DDR4_A12
IO_L6N_T0U_N11_AD6N_64
AC6
PL_DDR4_A13
IO_L1N_T0L_N1_DBC_64
AD9
PL_DDR4_BA0
IO_T1U_N12_64
AH6
PL_DDR4_BA1
IO_L5N_T0U_N9_AD14N_64
AC7
PL_DDR4_RAS_B
IO_T2U_N12_64
AB5
PL_DDR4_CAS_B
IO_L5P_T0U_N8_AD14P_64
AB7
PL_DDR4_WE_B
IO_L11N_T1U_N9_GC_64
AF6
PL_DDR4_ACT_B
IO_L13N_T2L_N1_GC_QBC_64
AD4
PL_DDR4_CS_B
IO_L6P_T0U_N10_AD6P_64
AB6
PL_DDR4_BG0
IO_L2N_T0L_N3_64
AE8
PL_DDR4_RST
IO_L7P_T1L_N0_QBC_AD13P_64
AG9
PL_DDR4_CLK_N
IO_L10N_T1U_N7_QBC_AD4N_64
AG5
PL_DDR4_CLK_P
IO_L10P_T1U_N6_QBC_AD4P_64
AG6
PL_DDR4_CKE
IO_T3U_N12_64
AE4
PL_DDR4_OTD
IO_L19N_T3L_N1_DBC_AD9N_64
AH4
Part 2.4: QSPI Flash
The FPGA core board ACU4EV is equipped with one 256MBit Quad-SPI
FLASH chip to form an 8-bit bandwidth data bus, the flash model is
MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard. Due to
the non-volatile nature of QSPI FLASH, it can be used as a boot device for the
system to store the boot image of the system. These images mainly include
FPGA bit files, ARM application code, and other user data files. The specific
models and related parameters of QSPI FLASH are shown in Table 2-4-1.
Position
Model
Capacity
Factory
U5
MT25QU256ABA1EW9
256Mbit
Winbond
Table 2-4-1: QSPI FLASH Specification