ZYNQ Ultrascale + FPGA Board AXU4EV-E User Manual
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The pin assignment of M.2 interface ZYNQ is as follows:
PCIE Data Transmit Positive
PCIE Data Transmit Negative
PCIE Data Receive Positive
PCIE Data Receive Negative
PCIE Reference Clock Positive
PCIE Reference Clock Negative
Part 3.3: DP Interface
The AXU4EV-E development board has a standard DisplayPort output
display interface for video image display. The interface supports VESA
DisplayPort V1.2a output standard, up to 4K x 2K@30Fps output, supports
Y-only, YCbCr444, YCbCr422, YCbCr420 and RGB video formats, each color
supports 6, 8, 10, or 12 bits.
The DisplayPort data transmission channel is directly driven and output by
the BANK505 PS MGT of ZU4EV, and the LANE2 and LANE3 TX signals of
MGT are connected to the DP connector in a differential signal mode. The
DisplayPort auxiliary channel is connected to the MIO pin of the PS. The
schematic diagram of the DP output interface design is shown in Figure 3-3-1:
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