ZYNQ Ultrascale + FPGA Board AXU4EV-E User Manual
Amazon Store: https://www.amazon.com/alinx
USB2.0 Data Direction Signal
Part 3.5: Gigabit Ethernet Interface
There are 2 Gigabit Ethernet ports on the AXU4EV-E carrier board, one is
connected to the PS end, and the other is connected to the PL end. The GPHY
chip uses Micrel's KSZ9031RNX Ethernet PHY chip to provide users with
network communication services. The KSZ9031RNX chip supports
10/100/1000 Mbps network transmission rate, and communicates with the
MAC layer of the ZU4EV system through the RGMII interface. KSZ9031RNX
supports MDI/MDX adaptation, various speed adaptation, Master/Slave
adaptation, and MDIO bus for PHY register management.
When the KSZ9031RNX is powered on, it will detect the level status of
some specific IOs to determine its own operating mode. Table 3-5-1 describes
the default settings after the GPHY chip is powered on.
MDIO/MDC Mode PHY Address
Enable 125Mhz clock output selection
LED light mode configuration
Link adaptation and full duplex
configuration
10/100/1000 adaptive, compatible
with full-duplex, half-duplex
Table 3-5-1: PHY chip default configuration value
To Next Page
Loading...
