ZYNQ Ultrascale + FPGA Board AXU4EV-E User Manual
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When the network is connected to Gigabit Ethernet, the data transmission
of ZYNQ and PHY chip KSZ9031RNX is communicated through the RGMII bus,
the transmission clock is 125Mhz, and the data is sampled on the rising edge
and falling samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of
ZYNQ and PHY chip KSZ9031RNX is communicated through RMII bus, and
the transmission clock is 25Mhz. Data is sampled on the rising edge and falling
samples of the clock.
Figure 3-5-1: ZYNQ PS system and GPHY connection diagram
The Gigabit Ethernet pin assignments are as follows:
Ethernet 1 RGMII Transmit Clock
Ethernet 1 Transmit data bit0
Ethernet 1 Transmit data bit1
Ethernet 1 Transmit data bit2
Ethernet 1 Transmit data bit3
Ethernet 1 Transmit Enable Signal
Ethernet 1 RGMII Receive Clock
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