ZYNQ Ultrascale + FPGA Board AXU4EV-E User Manual
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MIPI interface pin assignment
MIPI Input Clock Positive
MIPI Input Clock Negative
MIPI Input Date LANE0 Positive
MIPI Input Date LANE0 Negative
MIPI Input Date LANE1 Positive
MIPI Input Date LANE1 Negative
Part 3.12: JTAG Debug Port
The JTAG interface is reserved on the AXU4EV-E expansion board for
downloading ZYNQ UltraScale+ programs or firmware programs to FLASH. In
order to not damage the ZYNQ UltraScale+ chip by plugging and unplugging
under power, we aded a protection diode to the JTAG signal to ensure that the
signal voltage is within the range accepted by the FPGA and avoid damage to
the ZYNQ UltraScale+ chip.
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