Alinx AXU4EV-E - Part 3.10: 485 Communication Interface

ZYNQ Ultrascale + FPGA Board AXU4EV-E User Manual
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The CAN communication pin assignments are as follows:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
Description
PS_CAN1_TX
PS_MIO32
J16
CAN1 Transmitter
PS_CAN1_RX
PS_MIO33
L16
CAN1 Receiver
PS_CAN2_TX
PS_MIO39
H19
CAN2 Transmitter
PS_CAN2_RX
PS_MIO38
H18
CAN2 Receiver
Part 3.10: 485 communication interface
There are two 485 communication interfaces on the AXU4EV-E carrier
board. The 485 communication port 1 is connected to the IO interface of
BANK43~45 on the PL system. The 485 transceiver chip selects the MAX3485
chip from MAXIM for the user's 485 communication service.
Figure 3-3-1 is the connection diagram of the 485 transceiver chip on the
PL side
Figure 3-3-1: 485 Communication on the PL Side
The 485 communication pins are assigned as follows:
Signal Name
Pin Name
Pin Number
Description
PL_485_TXD1
B43_L1_N
AH10
The 1
st
Channel 485 Transceiver