ZYNQ Ultrascale + FPGA Board AXU4EV-E User Manual
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PL System Clock Source
The core board provides a differential 200MHz PL system clock source for
the reference clock of the DDR4 controller. The crystal oscillator output is
connected to the global clock (MRCC) of PL BANK64. This global clock can be
used to drive the DDR4 controller and user logic circuits in the FPGA. The
schematic diagram of this clock source is shown in Figure 2-6-4
Figure 2-6-4: PL system clock source
Clock pin assignment:
Part 2.7: LED
There is a red power indicator (PWR) and a configuration LED (DONE) on
the ACU4EV core board. When the core board is powered on, the power
indicator will light up; after the FPGA configuration program, the configuration
LED light will light up. The LED Schematic in the Core Board is shown in Figure
2-7-1:
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