91
7598H–AVR–07/09
ATtiny25/45/85
Figure 14-5. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR1A or OCR1B will
read the contents of the temporary location. This means that the most recently written value
always will read out of OCR1A or OCR1B.
When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C register, the out-
put PB1(OC1A) or PB3(OC1B) is held low or high according to the settings of
COM1A1/COM1A0. This is shown in Table 14-5.
In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C
value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is
set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to
the Timer Output Compare flags and interrupts.
The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See
the following equation:
Table 14-5. PWM Outputs OCR1x = $00 or OCR1C, x = A or B
COM1x1 COM1x0 OCR1x Output OC1x Output OC1x
0 1 $00 L H
0 1 OCR1C H L
1 0 $00 L Not connected.
1 0 OCR1C H Not connected.
1 1 $00 H Not connected.
1 1 OCR1C L Not connected.
PWM Output OC1x
PWM Output OC1x
Unsynchronized OC1x Latch
Synchronized OC1x Latch
Counter Value
Compare Value
Counter Value
Compare Value
Compare Value changes
Glitch
Compare Value changes
f
PWM
f
TCK1
OCR1C + 1()
------------------------------------=
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