Atmel ATtiny25 User Manual

98
7598H–AVR–07/09
ATtiny25/45/85
Figure 16-3. Three-wire Mode, Timing Diagram
The Three-wire mode timing is shown in Figure 16-3. At the top of the figure is a USCK cycle ref-
erence. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The
USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI
is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative
edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., sam-
ples data at negative and changes the output at positive edges. The USI clock modes
corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 16-3.), a bus transfer involves the following steps:
1. The Slave device and Master device sets up its data output and, depending on the pro-
tocol used, enables its output driver (mark A and B). The output is set up by writing the
data to be transmitted to the Serial Data Register. Enabling of the output is done by set-
ting the corresponding bit in the port Data Direction Register. Note that point A and B
does not have any specific order, but both must be at least one half USCK cycle before
point C where the data is sampled. This must be done to ensure that the data setup
requirement is satisfied. The 4-bit counter is reset to zero.
2. The Master generates a clock pulse by software toggling the USCK line twice (C and
D). The bit value on the slave and master’s data input (DI) pin is sampled by the USI on
the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit
counter will count both edges.
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that
the transfer is completed. The data bytes transferred must now be processed before a
new transfer can be initiated. The overflow interrupt will wake up the processor if it is set
to Idle mode. Depending of the protocol used the slave device can now set its output to
high impedance.
16.2.2 SPI Master Operation Example
The following code demonstrates how to use the USI module as a SPI Master:
SPITransfer:
sts USIDR,r16
ldi r16,(1<<USIOIF)
sts USISR,r16
ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
SPITransfer_loop:
sts USICR,r16
lds r16, USISR
sbrs r16, USIOIF
MSB
MSB
654321LSB
1 2 3 4 5 6 7 8
654321LSB
USCK
USCK
DO
DI
DCBA E
CYCLE
( Reference )

Atmel ATtiny25 Specifications

General

Architecture	AVR
Flash Memory	2 KB
SRAM	128 B
EEPROM	128 B
Clock Speed	20 MHz
I/O Pins	6
PWM Channels	2
Operating Voltage	1.8V - 5.5V
ADC	4 channels, 10-bit
Communication Interfaces	SPI, I2C, USART
Operating Temperature Range	-40°C to 85°C
Timers	8-bit Timer/Counter with PWM, 16-bit Timer/Counter with PWM
Package	8-pin PDIP, SOIC-8

Summary

Features

Overview and Pin Configurations

Pinout

Pin configuration details for ATtiny25/45/85, showing pin functions for SOIC and QFN packages.

Overview

Introduces the ATtiny25/45/85 as a low-power AVR microcontroller with RISC architecture.

AVR CPU Core

Architecture & Registers

Covers CPU core, architectural overview, ALU, status, and general purpose registers.

Instruction Execution & Reset/Interrupts

Details instruction timing, reset, and interrupt handling mechanisms.

ATtiny25/45/85 Memories

Flash, SRAM, EEPROM, and I/O Memory

Describes Flash, SRAM, EEPROM, and I/O memory spaces and their characteristics.

System Clock and Clock Options

Clock Sources and Prescalers

Details clock sources (RC, Crystal, PLL) and the system clock prescaler.

Power Management and Sleep Modes

MCU Control Register

Details the MCU Control Register for power management and sleep mode selection.

Sleep Modes (Idle, ADC Noise Reduction, Power-down)

Explains the different sleep modes and their features for power saving.

Power Reduction Register

Describes the PRR for stopping clocks to peripherals to reduce power consumption.

System Control and Reset

Reset Sources

Lists and describes the various reset sources like Power-on, External, Watchdog, and Brown-out.

Brown-out Detection

Details the On-chip Brown-out Detection (BOD) circuit and its configuration.

Interrupts

Interrupt Vectors in ATtiny25/45/85

Lists the interrupt vectors and their definitions for ATtiny25/45/85.

I/O Ports

Ports as General Digital I/O

Covers port configuration, general I/O, and switching between input/output.

Alternate Port Functions

Explains alternate functions of port pins and overriding signals.

Register Description for I/O-Ports

Details the PORTB, DDRB, and PINB registers for I/O port control.

External Interrupts

MCU Control Register – MCUCR

Details the External Interrupt Control Register for interrupt sense control.

General Interrupt Mask Register – GIMSK

Covers the GIMSK for enabling external and pin change interrupts.

8-bit Timer/Counter0 with PWM

Modes of Operation and Registers

Explains operational modes and register descriptions for Timer/Counter0.

Counter and Compare Units

Timer/Counter1 and Dead Time Generator

Details Timer/Counter1 operation and the Dead Time Generator for PWM.

Universal Serial Interface – USI

Functional Descriptions and Registers

Covers USI modes (3-wire, SPI, 2-wire) and register descriptions.

Analog Comparator

ACSR and ADCSRB Registers

Details Analog Comparator Control and Status Registers for configuration and interrupts.

Analog Comparator Multiplexed Input

Explains selecting ADC pins as the negative input to the Analog Comparator.

Analog to Digital Converter

ADC Features and Operation

Lists ADC features and describes its operation, including channel and reference selection.

Starting a Conversion

Explains manual and auto-triggered ADC conversion start methods.

ADC Conversion Result

Details how to read and interpret ADC conversion results in different modes.

debugWIRE On-chip Debug System

Features, Interface, and Registers

Covers debugwire features, physical interface, limitations, and registers.

Memory Programming

Lock Bits and Fuse Bytes

Explains memory lock bits and the functionality of fuse bytes.

Serial Downloading

Details serial programming methods including SPI and HVSP.

High-voltage Serial Programming

Covers programming Flash, EEPROM, Lock bits, and Fuse bits using HVSP.

Electrical Characteristics

Absolute Maximum Ratings*

Lists the stress ratings that may cause permanent damage to the device.

DC Characteristics

Provides DC characteristics across temperature and voltage ranges.

Typical Characteristics

Supply Current (Active, Idle, Power-down)

Shows supply current graphs for different modes versus frequency and VCC.

Pin Characteristics (Pull-up, Driver Strength, Thresholds)

Details pin pull-up, driver strength, and threshold characteristics.

Oscillator and BOD Characteristics

Covers BOD thresholds and internal oscillator frequency characteristics.

Register Summary

Instruction Set Summary

Ordering Information

Package Types

Lists available package types like T5 and PC with their specifications.

Document Revision History

Errata