144
7679H–CAN–08/08
AT90CAN32/64/128
• Bit 2 – OCFnB: Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register B (OCRnB).
Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB flag.
OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
• Bit 1 – OCFnA: Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register A (OCRnA).
Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA flag.
OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCFnA can be cleared by writing a logic one to its bit location.
• Bit 0 – TOVn: Timer/Counter Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOVn flag is set when the timer overflows. Refer to Table 13-4 on page 138 for the TOVn
flag behavior when using another WGMn3:0 bit setting.
TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed.
Alternatively, TOVn can be cleared by writing a logic one to its bit location.
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