157
7679H–CAN–08/08
AT90CAN32/64/128
Figure 14-12 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
Figure 14-12. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (f
clk_I/O
/8)
14.9 8-bit Timer/Counter Register Description
14.9.1 Timer/Counter2 Control Register A– TCCR2A
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when
operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare
match is forced on the Waveform Generation unit. The OC2A output is changed according to its
COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the
value present in the COM2A1:0 bits that determines the effect of the forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
Bit 7 6 5 4 3 2 1 0
FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 TCCR2A
Read/Write W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
To Next Page
Loading...
Need help?
General
