96
7679H–CAN–08/08
AT90CAN32/64/128
11. Timer/Counter3/1/0 Prescalers
Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to both
Timer/Counter3, Timer/Counter1 and Timer/Counter0.
11.1 Overview
Most bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number.
11.1.1 Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
CLK_I/O
). Alternatively, one of four taps from the prescaler can be used as a
clock source. The prescaled clock has a frequency of either f
CLK_I/O
/8, f
CLK_I/O
/64, f
CLK_I/O
/256, or
f
CLK_I/O
/1024.
11.1.2 Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter3, Timer/Counter1 and Timer/Counter0. Since
the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will
have implications for situations where a prescaled clock is used. One example of prescaling arti-
facts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The
number of system clock cycles from when the timer is enabled to the first count occurs can be
from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
11.1.3 External Clock Source
An external clock source applied to the T3/T1/T0 pin can be used as Timer/Counter clock
(clk
T3
/clk
T1
/clk
T0
). The T3/T1/T0 pin is sampled once every system clock cycle by the pin syn-
chronization logic. The synchronized (sampled) signal is then passed through the edge detector.
Figure 11-1 shows a functional equivalent block diagram of the T3/T1/T0 synchronization and
edge detector logic. The registers are clocked at the positive edge of the internal system clock
(
clk
I/O
). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clk
T3
/clk
T1
/clk
T0
pulse for each positive (CSn2:0 = 7) or nega-
tive (CSn2:0 = 6) edge it detects.
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