98
7679H–CAN–08/08
AT90CAN32/64/128
11.2 Timer/Counter0/1/3 Prescalers Register Description
11.2.1 General Timer/Counter Control Register – GTCCR
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR2 and PSR310 bits is kept, hence keeping the corresponding
prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted
and can be configured to the same value without the risk of one of them advancing during con-
figuration. When the TSM bit is written to zero, the PSR2 and PSR310 bits are cleared by
hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR310: Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0
When this bit is one, Timer/Counter3, Timer/Counter1 and Timer/Counter0 prescaler will be
Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note
that Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset
of this prescaler will affect these three timers.
Bit 7 6 5 4 3 2 1 0
TSM
– – – – – PSR2 PSR310 GTCCR
Read/Write R/W R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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