34
AT90S2313
0839G–08/01
rupts must be disabled during access from the main program or interrupts if interrupts
are re-enabled.
• TCNT1 Timer/Counter1 Write:
When the CPU writes to the high byte TCNT1H, the written data is placed in the
TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is
combined with the byte data in the TEMP register, and all 16 bits are written to the
TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte
TCNT1H must be accessed first for a full 16-bit register write operation.
• TCNT1 Timer/Counter1 Read:
When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent
to the CPU and the data of the high byte TCNT1H is placed in the TEMP register.
When the CPU reads the data in the high byte TCNT1H, the CPU receives the data
in the TEMP register. Consequently, the low byte TCNT1L must be accessed first
for a full 16-bit register read operation.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read
and write access. If Timer/Counter1 is written to and a clock source is selected, the
Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-
ten value.
Timer/Counter1 Output
Compare Register A –
OCR1AH and OCR1AL
The output compare register is a 16-bit read/write register.
The Timer/Counter1 Output Compare Register contains the data to be continuously
compared with Timer/Counter1. Actions on compare matches are specified in the
Timer/Counter1 Control and Status registers.
Since the Output Compare Register (OCR1A) is a 16-bit register, a temporary register
TEMP is used when OCR1A is written to ensure that both bytes are updated simulta-
neously. When the CPU writes the high byte, OCR1AH, the data is temporarily stored in
the TEMP register. When the CPU writes the low byte, OCR1AL, the TEMP register is
simultaneously written to OCR1AH. Consequently, the high byte OCR1AH must be writ-
ten first for a full 16-bit register write operation.
The TEMP register is also used when accessing TCNT1, and ICR1. If the main program
and interrupt routines perform access to registers using TEMP, interrupts must be dis-
abled during access from the main program or interrupts if interrupts are re-enabled.
Bit 151413121110 9 8
$2B ($4B) MSB OCR1AH
$2A ($4A) LSB OCR1AL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
00000000
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