Cavli Wireless C100QM - 3.16 ADC Interface; 3.17 RF Interface

Cavli Wireless C100QM/C10QM Hardware Manual
63
This interface is mainly used to connect the MCLK of the CODEC chip. The main clock
frequency of the NAU8810 is supported by default.
Table 3-22 CLK Pin Definition
NO.
Signal
name
I/O
description
paramete
r
Level value (V)
remarks
min
Typica
l
max
116
MCLK
D0
I2S master
clock
VOH
1.35
1.8
2
The default
output is
12.288M
VOL
0
0.45
3.16 ADC interface
The C100QM/C10QM provides two analog-to-digital converter interfaces to read the
voltage value. The ADC interface input voltage cannot exceed VBAT. It is recommended
that the ADC pin be input with a voltage divider circuit.
Table 3-23 ADC Pin Definitions
NO.
Signal
name
description
paramete
r
Level value (V)
remarks
min
Typi
cal
max
44
ADC1
Analog to digital
converter interface
1
VIN
0.3
VBAT
ADC
resolution
15Bits
45
ADCO
Analog to digital
converter interface
0
VIN
0.3
VBAT
ADC
resolution
15Bits
3.17 RF interface
The C100QM/C10QM module provides three antenna interfaces, one main set antenna