Cavli Wireless C100QM - 3.14 SPI Interface; Multiplexed I2 S Interface

Cavli Wireless C100QM/C10QM Hardware Manual
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possible interference lines.
✧ The spacing between the SDIO signal and other signals needs to be greater than 2
times the line width and ensure that the bus load is less than 40pF;
✧ Add a pull-up resistor to the SDIO signal with a resistance range of 10~100kΩ, a
recommended value of 100kΩ, and pull up to the VDD_SDIO pin of the module.
✧ To ensure good ESD performance, it is recommended to add a TVS tube to the SD
card pin and place it near the pin.
3.14 SPI interface / multiplexed I2S interface
The C100QM/C10QM provides an SPI interface with a maximum clock rate of 50MHz. In
addition, the module can only be used as the master, and the interface voltage domain is
1.8V.
Table 3-20 SPI Pin Definitions
NO.
Signal
name
I/O
descriptio
n
paramet
er
Level value (V)
remarks
min
Typica
l
max
37
SPI_CS_N
D0
SPI chip
selection
VOH
1.35
1.8
2
Multiplexing
I2S_D1
VOL
0
0.45
38
SPI_MOSI
DO
SPI data
output
VOH
1.35
1.8
2
Reuse
I2S_WS
VOL
0
0.45
39
SPI_MISO
DI
SPIO data
input
VIH
1.2
1.8
2
Multiplexing
I2S_DO
VIL
-0.3
0.6
40
SPI_CLK
DO
SPI clock
VOH
1.35
1.8
2
Multiplexing
I2S_CLK
VOL
0
0.45
The SPI interface of the C100QM/C10QM module can also be used as I2S. It can be