Technical description
4-16 HF SSB Transceiver 9323/9360/9390/9780 Technical Service Manual
The input to comparator pin 4 is from the prescaler IC9. This is divided down to
2 kHz by one of the programmable dividers. The quartz crystal (Z3) connected
between pins 7 and 8 forms the reference oscillator. It is set to a frequency of
7304 kHz. The second divider is programmed to always divide the reference
frequency down to 2 kHz.
The two divided signals are applied to the phase comparator internal to IC10.
When the two signals are "locked" in phase, the comparator output (pin 1) is at
mid-rail (2.5 V). These two frequencies are locked together by the action of the
loop, e.g. changing the first programmable divider will change the VCO
frequency.
Two separate outputs are available from the phase comparator. The output of IC10
pin 2 (PDB line) is a course control that outputs a mark:space ratio proportional to
the frequency difference between the divided signals. The output of IC10 pin 1
(PDA line) is the fine control. It gives an analogue output that takes over from the
PDB output when the two signals are close to phase lock.
The transistors V11, V12, V13 and associated components form the loop filter.
The input at the base of V13 is biased to 2.5 V by H1 (functioning as a zener
diode). The output DC, which can swing between ground and the positive rail
(26 V), is applied via L32 to the varicaps D20 to D23.
The components L32 and C95 provide an LPF to the control DC while presenting
a high impedance to the oscillator circuit. The control DC level changes the
capacity of the varicaps to set the VCO to the required frequency. As the control
voltage rises so does the frequency of the VCO.
When a new channel is selected, the microprocessor changes the value of the
programmable divider IC10, which is fed by the prescaler IC9. As the two signals
driving the phase comparator are now no longer at the same frequency, the phase
comparator outputs pulses to the loop filter. The output of the loop filter ramps in
the direction necessary to re-establish lock.
VCO1 and phase lock loop (04-03135)
1 04-03135 Sheet 1
The oscillator VCO1 is designed around a differential amplifier consisting of
FETs V8 and V9. The frequency of oscillation is determined by the tuned circuit
L33, C94 and the capacitance of the varicaps D20 to D23. The oscillator output
power is set by source resistors, R55 and R58. The resistor R54 assists in
maintaining a constant output level over the operating frequency range.
The oscillator output at the tap of the tuned inductor L33 is coupled via C101 to
an emitter follower V10. The output of V10 drives two mixers IC4 and IC5 via
C76 and C78 and a second emitter follower V11. The output of V11 is applied via
C104 and R66 to the input of synthesiser IC9 pin 4.
Synthesiser IC9 generates a DC control voltage via the phase/frequency detector
and control amplifier. This is applied to the varicaps to lock VCO1 to the
nominated frequency.
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