ConMed ExcaliburPLUS PC - Page 42

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ally-shifted out to the buffers U13A and U13B
one bit every 50 nanoseconds.
A3U14 is configured as a modulus 8 counter that
controls the parallel loading of the shift register
A3U17 and increments the lower waveform
address counter (A3U15 and A3U16). Both the
loading and incrementing occur on the rising
edge of the 20 MHz clock when /SRLOAD
(U14-11) goes low and then high. A3U14 also
generates 2.5 MHz and 10 MHz clocks from the
20 MHz oscillator Y1 for clocking the
Display/Keyboard Driver/Encoder A2U2 and the
microprocessor A3U3.
Each time /SRLOAD goes low and then high,
the lower waveform address counter formed by
A3U15 and A3U16 advances its count. The out-
puts from this counter (A0-A7) select the next 8
bit word to be loaded into A3U17 from A3U18.
When the lower waveform address counter reach-
es it full count, i.e., the entire waveform has been
completely output, /CNTRLD goes low on the
next count and the address counter is preloaded
to the pattern presented to it by O0-O7 of
A3U18. This pattern sets the modulus of the
address counter and thus the length of the wave-
form bit pattern. /CTRLOAD also clears the shift
register A3U17 to zeros to prevent putting the
modulus pattern out to the power amplifier. Since
/CTRLOAD is low only at the beginning of a
waveform, it is an excellent point to use for a
scope trigger when examining waveforms (use
TP20).
U13 provides both buffer and enable functions
for the waveform generator. U6D and U8C con-
trol the latch of the waveform.
3.3.8 Tone Generator
Schematic 4.4b contains the Tone Generator. It is
a voltage controlled current source that is
switched on and off at the frequency of the
desired tone. /TONE is generated by the micro-
processor A3U3 at the desired audio frequency
and is buffered by sections of A3U5 and A3U12
to generate the signal SPKR-. When SPKR- is
inactive, no current flows through speaker
A8SP1, thus there is no sound. When SPKR- is
low, the current flow through the speaker is deter-
mined by R16 and the base voltage of A3Q2.
A9R1(the volume control pot) and A3R18 form
a voltage divider to set the base voltage of A3Q2.
The emitter voltage of A3Q2 is one diode drop
higher than its base voltage and is a constant for a
given base voltage. This controlled emitter volt-
age across R15 means a current is flowing
through A3Q2 that can be controlled by the base
voltage. That is how the volume is set for normal
operation. When an alarm is sounded, /LOUD
from the microprocessor (which is buffered by
sections of U5 and U12) forces the base voltage
of A302 into saturation regardless of the setting
of the volume control pot. This is to assure that
an alarm cannot be turned down in volume.
3.3.9 Base Voltage Monitor
R55,R60,R61,R62,D8,C72, and U26:A form a
+5 Volt Overvoltage shutdown circuit. When the
+5 Vde supply rises above 5.4 Vdc, U26-2 forces
the base of A8Q1 low which causes VBASE to
turn off.
R63,R64,R71,C69 and U26:B form a Base
Voltage Check circuit. The DAC at UI9 is con-
trolled by the microprocessor (with interrupts dis-
abled to ignore /IFAIL) to produce a VBase refer-
ence voltage for power up self tests and at least
once every 500 mSec for each mode of operation
and power setting when power is on during nor-
mal operation. When RF is activated and the
resulting voltage exceeds the reference input volt-
age provided by the DAC UI9, VBASHI will go
high. This input is then read by the microproces-
sor, and if high, causes a fatal error that produces
an “Err 22.2” code and shuts down the Excalibur
Plus PC. Power On Self Test Errors are “Err
22.0” if the VBase voltage is too low and “Err
22.1” if the VBase voltage is too high. Although
it is possible for these errors to occur because of a
temporary fault condition and may be recoverable
by cycling power, it generally occurs because of a
problem in the Excalibur Plus PC circuitry and
should be checked by the Biomedical Department
before returning the unit to service.
3.3.10 Waveform Monitor
R67,C70 and U26:C form an Average Waveform
Check circuit while R65,R66,C74 and U27 form
a Duty Cycle to Voltage circuit. The DAC at UI9
is controlled by the microprocessor (with inter-