106 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
9.1.2.1 I2C_CONFIG register
The I2C_CONFIG register is used to configure I2C interface parameters and to enable the block.
9.1.2.2 I2C_STATUS register
The I2C_STATUS register provides the current transfer status for the I2C interface.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0DMA_MODERRW0
0: Register-based transfers
1: DMA-based transfers
2 I2C_100KHz R RW 1
1: I2C is in the 100-KHz mode, use clock with
50% duty cycle.
0: Other speeds, use 40% duty cycle.
29 RX_CLEAR R RW 0
0: Do nothing
1: Clear receive FIFO
Firmware must wait for RX_DATA = 0 before
clearing this bit after it is set.
30 TX_CLEAR R RW 0
0: Do nothing
1: Clear transmit FIFO
Use only when ENABLE = 0; behavior unde-
fined when ENABLE = 1
Once TX_CLEAR is set, firmware must wait for
TX_DONE before clearing it.
31 ENABLE R RW 0
Enable block here, but only after all other con-
figuration is set. Do not set this bit to 1 while
changing any other configuration value in this
register.
Disabling the block resets all I
2
C controller
state machines and stops all transfers at the
end of current byte. When DMA_MODE=1,
data hanging in the transmit pipeline may be
lost. Any unread data in the ingress data regis-
ter is lost.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_DONE W R 0
Indicates receive operation completed. Non
sticky.
1RX_DATAWR 0
Indicates data is available in the RX FIFO. Only
relevant when I2C_CONFIG.DMA_MODE=0.
This bit is updated immediately after reads from
INGRESS_DATA register. Non sticky
2RX_HALFWR 0
Indicates that the RX FIFO is at least half full.
Only relevant when I2C_CONFIG.DMA_MODE
= 0.
This bit is updated immediately after reads from
INGRESS_DATA register. Non sticky
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