FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 99
9. FX3 Serial Peripheral Register Access
9.1 Serial Peripheral (LPP) Registers
The EZ-USB FX3 device implements a set of serial peripheral interfaces (I2S, I
2
C, UART, and SPI)
that can be used to talk to other devices. This chapter lists the FX3 device registers that provide con-
trol and status information for each of these interfaces.
9.1.1 I2S Registers
The I2S interface on the FX3 device is a master interface that is can output stereophonic data at dif-
ferent sampling rates. This section documents the control and status registers related to the I2S
interface.
9.1.1.1 I2S_CONFIG Register
The I2S_CONFIG register configures the operating modes for the I2S master interface on the FX3
device.
Name Width (bits) Address Description
I2S_CONFIG 32 0xE0000000 Configurations and modes register
I2S_STATUS 32 0xE0000004 Status register
I2S_INTR 32 0xE0000008 Interrupt request (status) register
I2S_INTR_MASK 32 0xE000000C Interrupt mask register
I2S_EGRESS_DATA_LEFT 32 0xE0000010 Left channel egress data register
I2S_EGRESS_DATA_RIGHT 32 0xE0000014 Right channel egress data register
I2S_COUNTER 32 0xE0000018 Sample counter register
I2S_SOCKET 32 0xE000001C Socket register
I2S_ID 32 0xE00003F0 Block Id register
I2S_POWER 32 0xE00003F4 Power, clock and reset control register
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0PAUSE R RW0
Pause transmission, transmit 0s.
Setting this bit to 1 does not discard any samples.
Clearing the bit resumes data at the same position.
A small, integral, but undefined number of samples
are transmitted after this bit is set to 1 (to ensure no
hanging samples).
1MUTE R RW1
Discard the value read from the DMA and, instead,
transmit zeros. Continue to read input samples at
normal rate.
2 ENDIAN R RW 0
0: MSB First
1: LSB First
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